How to Choose a Semiconductor Foundry for an AI Chip

Choosing a semiconductor foundry means matching your AI chip’s performance, power, cost, manufacturing schedule, and production volume to a process the foundry can actually support. Before approaching candidates, define the chip’s workload and target market, estimate required volumes, and identify the technical and commercial constraints your team cannot compromise on.

What You’ll Need

• A product brief covering AI workloads, target users, deployment environment, and expected launch date.
• Initial estimates for compute, memory bandwidth and capacity, power, package, and chip size.
• Volume forecasts for engineering samples, launch, and later production, with low, expected, and high scenarios.
• A preliminary cost model that includes design, masks, wafers, packaging, testing, and engineering support.
• A cross-functional evaluation team spanning chip design, physical design, packaging, supply chain, finance, and product planning.
• Non-confidential questions for initial discussions; detailed design information should be shared only under suitable agreements and access controls.

Step-by-Step

1. Translate the product into measurable requirements. Describe the actual workloads: for example, inference or training, batch size, model and precision, latency target, throughput, and utilization. Define performance per watt, memory bandwidth, on-chip memory, interfaces, and operating conditions. Separate hard constraints from goals. A foundry cannot recommend a process meaningfully if “fast AI chip” is the only specification.
2. Decide what you are asking the foundry to manufacture. Some foundries provide wafer fabrication, while other parts of the supply chain may provide design enablement, packaging, assembly, or testing. Determine whether your project needs a monolithic die, chiplets, a particular memory integration approach, or advanced packaging. Identify which services the foundry offers directly and which depend on partners. Confirm responsibilities and handoffs rather than assuming “foundry support” covers the whole path.
3. Shortlist processes using evidence, not node names. Compare process options against your design’s likely logic density, frequency, leakage, power, analog or I/O needs, and manufacturing maturity. A smaller nominal process node does not automatically mean a cheaper, faster, or more energy-efficient finished chip. Ask for current design rules, available libraries, memory compilers, I/O options, and relevant process data under appropriate confidentiality terms. Check that the process is available to your design team and compatible with its tools and schedule.
4. Check design enablement and support. Ask whether the required process design kit, standard-cell libraries, SRAM macros, interface IP, and verification collateral are available and qualified for your intended use. Establish which EDA tools and versions are supported, what signoff requirements apply, and how often collateral changes. Ask who will handle technical questions, how issues are escalated, and whether support is available during critical design milestones. Missing or immature IP can erase the theoretical benefit of a process.
5. Evaluate packaging, memory, and system integration early. AI accelerators can be limited by memory capacity, bandwidth, power delivery, and thermal behavior rather than compute alone. Compare feasible package options, interconnects, substrate needs, and availability of required memory components. Clarify whether packaging and test are performed by the foundry or an outside provider, and who owns schedule coordination and yield analysis. Validate the complete package-and-board concept; a promising die plan may fail at system level.
6. Model cost and yield across your volume range. Request comparable quotations and assumptions for engineering lots and production, including masks, wafers, test, packaging, and any non-recurring engineering charges. Ask how die area, process complexity, and package choice affect cost. Foundries may not disclose detailed yield information, but you can ask about process maturity, qualification status, yield-learning plans, and the basis for any estimates. Compare total cost per usable device—not just wafer price—and stress-test the model at low and high volumes.
7. Verify capacity, lead times, and supply resilience. Ask what capacity can be allocated to your product, what commitments are conditional, and how forecasts, order windows, and cancellations work. Distinguish quoted lead times from guaranteed commitments. Discuss allocation priorities, geographic concentration, disruption planning, and whether a second source is technically realistic. A second foundry often requires substantial redesign and requalification, so do not treat it as an instant fallback.
8. Review quality, qualification, and change control. Match the foundry’s manufacturing and quality processes to the product’s intended application and customer requirements. Ask how process changes are communicated, how lots are traced, and how defects or excursions are investigated. Confirm the qualification plan for the die, package, and finished device, including who pays for and approves each step. Avoid relying on general claims when your customers require specific evidence or documented procedures.
9. Assess commercial terms and information handling. Have qualified legal and procurement teams review confidentiality, intellectual-property ownership, data access, export or geographic restrictions that apply to your project, liability, cancellation, and change terms. Check what design files and production data each party can access. Compare the full agreement and operating model, not only the headline quote. Keep sensitive design details limited to the people and systems authorized to receive them.
10. Run a structured decision and reduce risk before committing. Score candidates against weighted criteria: technical fit, schedule, cost, support, packaging, capacity, quality, and resilience. Record evidence, assumptions, unresolved questions, and the owner for each follow-up. Before a major commitment, test the riskiest assumptions through a design-technology assessment, early physical-design study, package feasibility review, or other milestone appropriate to the project. Choose the option that meets the product’s constraints with manageable risk—not simply the most advanced process.

Common Mistakes

• Choosing by node label alone: Process names are not a reliable, like-for-like measure across foundries. Compare actual process capabilities and design collateral.
• Optimizing only for peak compute: Memory traffic, power delivery, cooling, and package limits can constrain real application performance.
• Ignoring total program cost: Mask costs, engineering time, IP, package development, test, and yield all affect the economics.
• Assuming a quoted schedule is guaranteed: Clarify dependencies, capacity reservation, engineering-lot timing, and what happens when milestones slip.
• Waiting to consider packaging: Late package decisions can force changes to die layout, interfaces, power delivery, and thermal design.
• Assuming a second source is interchangeable: Different processes usually require design adaptation, validation, and qualification.

Tips

• Use the same request-for-information template and assumptions for every candidate, then document differences in what each quote includes.
• Present volume as scenarios and update forecasts as customer demand becomes clearer.
• Ask for a named technical contact and an escalation path before the project reaches a schedule-critical stage.
• Have system, package, and silicon teams review the same performance and power assumptions.
• Keep a decision log so later changes in cost, capacity, or process readiness can be compared with the original rationale.

Troubleshooting

• No candidate supports the full requirement: Separate essential requirements from preferences. Revisit precision, interfaces, die partitioning, package, or launch timing, then ask candidates which specific change would make the design feasible.
• Design enablement is delayed: Get a written list of missing collateral, delivery dates, and interim restrictions. Estimate the impact on design and signoff; do not base a tape-out schedule on unvalidated files.
• Cost estimates differ sharply: Normalize die size, volume, package, test coverage, yield assumptions, and included engineering services. Ask each provider to explain its assumptions before comparing totals.
• Capacity cannot be confirmed: Request the conditions for allocation in writing and ask what forecast or commitment is required. Maintain a schedule contingency and evaluate redesign options early.
• Early silicon misses targets: Use measured results to distinguish process variation from design, package, memory, or board issues. Agree on a joint failure-analysis and corrective-action process before ordering the next lot.

Frequently Asked Questions

Does an AI chip always need the newest process node?
No. The best choice depends on workload, power, die area, memory and I/O needs, process maturity, cost, and availability. Benchmark realistic designs where possible.

Should a startup choose a large foundry or a smaller one?
Compare the specific process, design support, capacity, packaging access, and commercial terms. Company size alone does not show whether a candidate fits your project.

Can I compare wafer prices directly?
Only when assumptions match. Wafer price does not include all costs, and the usable-die count depends on die area and yield. Compare the full cost per tested, packaged device.

When should packaging be selected?
Early in architecture and foundry evaluation. Package constraints can affect memory bandwidth, power delivery, thermal performance, die design, cost, and schedule.

Can I move a design to another foundry if the first one slips?
Usually not without changes. Process rules, libraries, IP, and signoff requirements differ, so a move may require redesign and requalification.

What should I ask before signing a production agreement?
Confirm capacity and forecast obligations, pricing assumptions, quality and change-control processes, delivery terms, data handling, responsibilities for packaging and test, and remedies for schedule or quality problems. Have appropriate legal and procurement specialists review the agreement.

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