TSMC 1nm Factory Plans: What We Know

Yes, TSMC has confirmed plans to build fabs for its 1nm-class (A10) process technology, with production targeted for the second half of 2028. The company has designated a site in the Taichung Science Park in Taiwan for the new facilities, though construction timelines and final capacity are still subject to regulatory approvals and market conditions.

Formula

The calculator above estimates two simple derived values from a target year and process node. The first output, Years from 2025, is simply the difference between the target year and 2025: Years = Year - 2025. The second output, Node generation, is the reciprocal of the process node in nanometers: Generation = 1 / Node (nm). This is not a physical formula but a way to see how many years away a target is and how the node number relates to feature size.

Worked Example

Using the default values: Year = 2028, Node = 1 nm.

• Years from 2025 = 2028 – 2025 = 3
• Node generation = 1 / 1 = 1

The calculator shows 3 years from 2025 and a generation value of 1 (meaning the node is 1 nm).

Background: TSMC’s Roadmap to 1nm

TSMC’s current leading-edge processes are the 3nm family (N3, N3E, N3P) and the upcoming 2nm (N2) slated for 2025 volume production. The company’s publicly stated roadmap includes a 1.4nm node (A14) and then the 1nm node (A10), named for the angstrom unit (1 Å = 0.1 nm). The A10 process is expected to use a new transistor architecture—likely gate-all-around (GAA) nanosheets, which TSMC already uses for N2, evolving to a complementary FET (CFET) design for further scaling.

The Taichung Science Park site, specifically the expansion area known as Taichung Science Park Phase 3, has been earmarked for the A10 fabs. TSMC has been acquiring land and preparing infrastructure since 2023, but formal construction awaits environmental impact assessment approvals and government permits. The company has also stated that it will decide on the final location based on water, power, and land availability, with overseas sites (like Arizona) not ruled out for future advanced nodes.

What Does “1nm” Actually Mean?

The “nm” in a process node no longer refers to a physical dimension like gate length or metal pitch. For nodes below 10nm, the number is largely a marketing label that indicates a generational step, not a measurement. For example, TSMC’s N5 (5nm) has a metal pitch of about 30nm, and N3 is not 3nm in any physical sense. The 1nm node (A10) will likely have a transistor density exceeding 300 million transistors per square millimeter, up from roughly 200 million for N3. The actual dimensions are determined by the design rules and the lithography wavelength (currently 13.5nm EUV), with multi-patterning and other tricks used to create features smaller than the wavelength.

Challenges in Building a 1nm Fab

Constructing a fab for 1nm-class chips is enormously complex. Key challenges include:

• Extreme ultraviolet (EUV) lithography: High-NA EUV tools from ASML are required, each costing over $300 million and weighing 150 tons. TSMC has ordered these tools but integrating them into a production line takes years.
• Power and water: A single leading-edge fab can consume up to 100 megawatts of electricity and 50,000 cubic meters of water per day. Taichung’s water supply has been a concern, especially after the 2021 drought.
• Chemical and material supply: Advanced nodes require ultra-pure chemicals, specialty gases, and silicon wafers with extreme flatness. Any supply chain disruption can delay ramp-up.
• Yield learning: Even after a fab is built, achieving acceptable yields (percentage of working chips per wafer) can take 2-3 years. TSMC’s N3 took about a year to reach a yield comparable to N5, and 1nm will likely be similar or longer.

Comparison with Rivals: Intel and Samsung

TSMC is not alone in the race to 1nm. Intel has announced its “18A” (1.8nm) and “14A” (1.4nm) nodes, targeting 2025 and 2027 respectively. Samsung Foundry has its own 2nm (SF2) and 1.4nm (SF1.4) plans, with production expected around 2027. However, TSMC holds a dominant market share (about 60% of the foundry market) and has a track record of delivering on its roadmap, though its 3nm ramp was slightly delayed. The 1nm node will be a test of whether TSMC can maintain its lead as physical limits approach.

Costs and Economic Viability

Building a 1nm fab is astronomically expensive. A single fab with a capacity of 50,000 wafer starts per month could cost $20-30 billion, including equipment and cleanroom construction. TSMC’s total capital expenditure for 2024 was around $30 billion, and the A10 fabs will require a significant share of that budget over several years. The cost per wafer at 1nm is expected to be 20-30% higher than at 3nm, which means chip prices for consumers will likely rise. However, the higher transistor density can reduce cost per function, so the economic benefit depends on the design.

Safety and Environmental Considerations

Semiconductor fabs use hazardous chemicals (e.g., arsine, phosphine, hydrofluoric acid) and require strict safety protocols. TSMC has a strong safety record, but the expansion in Taichung has raised environmental concerns. The company has committed to using 100% renewable energy by 2040 and has implemented water recycling systems that reuse about 85% of water in its fabs. For the new 1nm site, TSMC has pledged to meet or exceed all local environmental regulations, including waste treatment and emissions controls. Residents near the science park have expressed concerns about water consumption and air quality, and TSMC has held public briefings to address them.

Frequently Asked Questions

When will TSMC’s 1nm factory start production?

TSMC has targeted the second half of 2028 for volume production of its A10 (1nm) process. Construction of the Taichung facility is expected to begin in 2025-2026, but this depends on regulatory approvals and the finalization of equipment orders. Any delays in EUV tool delivery or yield ramp could push production to 2029.

Will the 1nm factory be in Taiwan or the US?

The first 1nm fabs are planned for Taichung, Taiwan. TSMC has not announced a 1nm fab in the US, though its Arizona plant will produce 4nm and 3nm chips starting in 2025. The US government has pushed for advanced nodes on American soil, but TSMC has said that the most advanced nodes will remain in Taiwan for now, citing the existing supply chain and engineering talent.

What products will use 1nm chips?

Likely candidates include high-end smartphones (e.g., future Apple A-series and Qualcomm Snapdragon chips), AI accelerators (like NVIDIA GPUs), and data center CPUs. The 1nm node will offer a significant performance-per-watt improvement, which is critical for mobile devices and power-hungry AI systems. It may also be used in advanced automotive chips for autonomous driving.

How does 1nm compare to 3nm in performance?

TSMC has not published official numbers, but based on historical trends, a full node shrink typically offers a 15-20% speed increase at the same power, or a 30-40% power reduction at the same speed, plus a 1.5-1.7x increase in transistor density. The 1nm node is expected to follow this pattern, but the actual gains will depend on the design and the specific transistor architecture used.

Is 1nm the end of Moore’s Law?

Not exactly. 1nm is approaching the physical limits of silicon transistors, but the industry has alternatives like stacked transistors (CFET), 2D materials (e.g., molybdenum disulfide), and advanced packaging (chiplet designs) that can continue scaling. TSMC has already discussed “Beyond 1nm” research, including using carbon nanotubes and other novel materials. So 1nm is a milestone, not a stop sign.

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in t | Year | - | 2028 | 2020 | 2035
in p | Process node (nm) | nm | 1 | 0.5 | 10
out y | Years from 2025 | years | t - 2025 | 1
out n | Node generation | - | 1 / p | 2