Why Samsung Foundry Trails TSMC: Yield Factors

Samsung Foundry trails TSMC primarily because of consistently lower manufacturing yields on advanced nodes, which stem from a combination of process design choices, customer trust, and execution history. Yield — the percentage of functional chips from a single wafer — directly determines cost and supply, and TSMC’s higher yields give it a decisive advantage in both price and reliability.

Formula

The calculator above works out your average pace and speed for a run, walk, or cycle. You enter the total time and the distance covered, and it returns the time per kilometer (or mile) and the average speed in km/h. The formulas are:

Pace = Time ÷ Distance

Speed = Distance ÷ (Time ÷ 60)

Where Time is in minutes, Distance is in kilometers, Pace is in minutes per kilometer, and Speed is in kilometers per hour. If you prefer miles, convert the distance to miles first (1 km = 0.621371 miles) and the pace will be in minutes per mile.

Worked Example

Using the default values from the calculator: Time = 30 minutes, Distance = 10 km.

Step 1: Calculate pace — 30 ÷ 10 = 3.0 minutes per kilometer.

Step 2: Calculate speed — 10 ÷ (30 ÷ 60) = 10 ÷ 0.5 = 20.0 km/h.

The calculator shows a pace of 3:00 min/km and a speed of 20.0 km/h. That is a very fast pace, typical of a professional runner, but the numbers are consistent.

Why Yield Matters

Yield is the percentage of dies on a wafer that pass testing and can be sold. A 90% yield means 90 out of 100 chips are good; a 50% yield means half are scrap. Lower yield raises the effective cost per chip because the wafer cost is fixed. For example, if a wafer costs $10,000 and yields 100 good chips, each costs $100. If yield drops to 50, each costs $200. That doubles the cost for the same wafer, making the product less competitive or less profitable.

Yield also affects supply. A fab with lower yield needs more wafers to meet the same demand, which strains capacity and delays deliveries. For a foundry, yield is the single most important metric because it determines both cost and volume.

How Samsung and TSMC Differ

Both companies use similar lithography and equipment, but their process architectures diverge. Samsung has historically used a gate-all-around (GAA) transistor design starting at its 3nm node, while TSMC stuck with FinFET until its 2nm node. GAA is theoretically superior, but it is harder to manufacture at scale. Samsung’s early GAA yields were reportedly low, causing customers to hesitate. TSMC’s more conservative approach allowed it to ramp 5nm and 4nm with higher yields, which attracted major customers like Apple, AMD, and Nvidia.

Another difference is customer relationships. TSMC works closely with each customer to optimize the process for their specific designs, a model called “co-optimization.” Samsung has tried similar programs but has fewer design wins, which means less feedback and slower learning. More volume leads to faster yield improvement because defects are found and fixed quicker.

Common Problems in Advanced Nodes

At 5nm and below, several physical challenges reduce yield:

• EUV (extreme ultraviolet) lithography — EUV is used for critical layers, but it is slow and has a higher defect rate than older DUV. Each EUV layer adds risk.
• Line edge roughness — The edges of tiny features are not perfectly smooth, which can cause short circuits or open circuits.
• Random defects — Particles, impurities, or slight variations in deposition can kill a chip. Smaller transistors are more sensitive to these.
• Thermal and stress issues — Stacking layers and using new materials can cause warping or cracks.

Samsung’s GAA design is more prone to some of these because the transistor structure is more complex. TSMC’s FinFET, while older, has been refined over many years, so its defect density is lower.

How to Choose a Foundry

For a chip designer, the choice of foundry depends on several factors:

• Yield and cost — Higher yield means lower cost per chip, which is critical for high-volume products like smartphones.
• Process maturity — A mature process has fewer surprises and better design kits.
• Capacity and timeline — Can the foundry deliver enough wafers when you need them?
• Design support — Does the foundry provide good libraries, IP, and engineering help?
• Strategic considerations — Some companies avoid putting all their eggs in one basket, but most still choose TSMC for advanced nodes.

For example, Qualcomm uses TSMC for its flagship Snapdragon chips, while Samsung’s Exynos chips are made in-house. This reflects the yield gap: Qualcomm switched back to TSMC after Samsung’s 5nm and 4nm yields were disappointing.

Costs and Pricing

Advanced node development costs are enormous. A single 5nm mask set can cost over $10 million, and a full tape-out (design submission) can exceed $50 million. These costs are only justified if yields are high enough to produce millions of chips. TSMC’s higher yields mean its customers can amortize design costs over more units, lowering the per-chip cost. Samsung, with lower yields, must charge more per chip or accept thinner margins, making it less attractive.

TSMC also spends heavily on R&D and capital equipment. In 2023, TSMC’s capital expenditure was around $30 billion, far more than Samsung Foundry’s. This investment goes into new tools, process development, and yield improvement, creating a virtuous cycle.

Safety and Reliability

Yield is not just about cost; it also affects reliability. Chips that pass testing but have marginal defects may fail later in the field. Lower yield processes tend to have more latent defects, increasing failure rates. For automotive, medical, and aerospace applications, reliability is critical. TSMC’s proven process record gives it an edge in these markets, while Samsung has had to work hard to qualify its processes for such strict standards.

Alternatives and the Future

Beyond TSMC and Samsung, Intel Foundry is attempting to re-enter the market, and China’s SMIC is developing older nodes. However, for leading-edge chips, TSMC remains the dominant choice. Samsung is investing heavily in its 2nm GAA process, hoping to catch up. If Samsung can improve yields, it could regain market share, but as of now, TSMC’s lead is substantial.

One common misconception is that Samsung’s lower yield is due to poor equipment or lack of skill. In reality, Samsung is a capable manufacturer; the gap is more about process architecture and customer feedback loops. TSMC’s incremental approach has proven more reliable than Samsung’s leap to GAA.

Frequently Asked Questions

Why is Samsung Foundry behind TSMC?
Samsung’s advanced nodes (5nm and 4nm) have had lower yields than TSMC’s, leading to higher costs and fewer customer orders. The root causes include a more aggressive switch to GAA transistors and less design co-optimization with customers.

What is a good yield for a modern chip?
For a mature advanced node, yields above 90% are considered good. Early in a node’s life, yields may be 50-70%, but they improve as the process is refined. TSMC’s 5nm reportedly achieved yields above 80% relatively quickly.

Does yield affect chip performance?
Not directly. Yield affects cost and availability, not the speed or power of the chip. However, lower yield may force a company to bin chips (sort by speed) more aggressively, which can reduce the number of high-performance parts.

Can Samsung catch up to TSMC?
It is possible but difficult. Samsung’s 3nm GAA is still ramping, and its 2nm is planned for 2025. Catching up requires not just technical success but also winning back customers, which takes years of consistent delivery.

Why do most companies choose TSMC over Samsung?
Most companies choose TSMC because it offers higher yields, better design support, and a proven track record. The risk of lower yield and potential delays outweighs any price advantage Samsung might offer.

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in t | Time to fill | min | 30 | 0
in d | Distance | km | 10 | 0 | 100000
out pace | Average pace | min/km | t / d | 2
out speed | Average speed | km/h | d / (t / 60) | 2